This application claims the priority benefit of Taiwan application serial no. 91100640,filed Jan. 17, 2002.
1. Filed of Invention
The present invention relates to semiconductor device. More particularly, the present invention relates to a metal oxide semiconductor field effect transistor (MOSFET) structure with reduced junction capacitance.
2. Description of Related Art
During a MOSFET device operation, the parasitic junction capacitance of a source/drain region is created at two sides of the depletion region between the source/drain region and the substrate. The junction capacitance is approximately proportional to the area of the source/drain region. Since the junction capacitance has to be charged and discharged each time the transistor switches between the logic states, therefore an increase in junction capacitance will unfavorably slow down the performance of the transistor, because an increased junction capacitance requires longer charging and discharging time.
FIG. 1 depicts a schematic top view of a conventional MOSFET device 18, showing a straight gate electrode 11, symmetric source/drain regions 12 and 13 formed in an active area 17. A plurality of contacts 14 and 15 can be formed above the source/drain regions 12 and 13, respectively.
Still referring to FIG. 1, a dash line 16 shown in the gate electrode 11 represents the width of a channel under the gate electrode 11, while a distance between the source/drain regions 12 and 13 represent the channel length (not indicated). In this case, the channel width determines the flux of the channel current generated between the source/drain regions 12 and 13. The flux is directly proportional to the channel current. In other words, when the channel width becomes smaller as the device is miniaturized, the channel current between the source/drain regions 12 and 13 decreases corresponding to the decrease in the channel width, slowing down performance of the device. Accordingly, it is highly desirable to provide a MOSFET structure having reduced size and while maintaining good device characteristics.
Accordingly, it is an object of the present invention to provide a semiconductor device structure having a smaller source/drain region, this would reduce the device junction capacitance, therefore, the performance of the device can be improved, which device satisfies the device miniaturization design rule.
It is another object of the present invention to provide a semiconductor device structure having a larger channel width, this would increase the channel current, thus the operation speed of device can be substantially improved.
Yet it is another object of the present invention to provide a semiconductor device having a gate structure, wherein the physical gate dimension is unaltered, and yet satisfies the device miniaturization design rule so that the integration of the device can be increased.
It is another object of the present invention to provide a method for forming a semiconductor device in accord with the above objects of the present invention, which method is also readily viable.
It is an object of the present invention to provide a method for forming a semiconductor device in accord with the above objects of the present invention, which method is also economical.
In accord with the above objects and other advantages of the present invention, a new MOSFET structure comprising a P-shape gate, smaller source/drain regions and a longer channel width is provided.
Specifically, the present invention provides a MOSFET structure comprising a P-shape gate, disposed over a semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the P-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the P-shape gate. Silicide structures are disposed on the source/drain regions.
In accord to an aspect of the present invention there is provided a MOSFET device having a P-shape gate structure. Because of the P-shape gate structure, there is a source region surrounding a shrunken drain region therefore, asymmetric source/drain regions with smaller areas can be formed. This makes it possible to further reduce the junction capacitance. And the size of the MOSFET device can be reduced, thereby increasing the integration of the IC device.
In accord to another aspect of the present invention is that because of the smaller source/drain regions, less contacts are required compared to a conventional MOSFET. Consequently, the area needed for a conductive layer to electrically connect with the contacts over the MOSFET can be smaller compared to the conventional MOSFET structure. Thus the integration of the IC device can be increased.
Yet in accord to an aspect of the present invention is that because of the P-shape gate, the channel width can be effectively increased. Because the channel width is increased, the channel current can be larger. Thus the operation speed of the MOSFET device can be substantially increased.
It is understood that the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the present invention.